1. Field of the Disclosure
The present disclosure relates to an array substrate for a liquid crystal display (LCD), and more particularly, to an array substrate having an oxide semiconductor layer having highly stable device characteristics and capable of inhibiting parasitic capacitance caused by overlap between a gate electrode and each of source/drain electrodes to improve resolution characteristics and the characteristics of a thin-film transistor (TFT).
2. Discussion of the Related Art
In recent years, with the advent of an information-oriented society, the field of display devices configured to process and display a large amount of information has rapidly been developed. Liquid crystal displays (LCDs) or organic light emitting diodes (OLEDs) have lately been developed as flat panel displays (FPDs) having excellent performance, such as a small thickness, light weight, and low power consumption, and superseded conventional cathode-ray tubes (CRTs).
Among LCDs, an active matrix (AM)-type LCD including an array substrate having a TFT serving as a switching element capable of controlling on/off voltages of each of pixels, may have excellent resolution and capability of displaying moving images.
The AM-type LCD often has TFTs serving as the switching device to turn on and off each of pixel regions.
FIG. 1 is a cross-sectional view of a conventional array substrate 11 of an LCD, which illustrates one pixel region of a TFT.
As shown in FIG. 1, a plurality of gate lines (not shown) and a plurality of data lines 33 may be formed on an array substrate 11, and a plurality of pixel regions P are defined by intersection of the gate lines and the data lines 33. A gate electrode 15 may be formed in a switch region TrA of each of the plurality of pixel regions P. Also, a gate insulating layer 18 may be formed on the entire surface of the resultant structure to cover the gate electrode 15, and a semiconductor layer 28 including an active layer 22 formed of intrinsic amorphous silicon (a-Si) and an ohmic contact layer 26 formed of impurity doped amorphous silicon may be sequentially formed on the gate insulating layer 18.
In addition, a source electrode 36 and a drain electrode 38 may be formed on the ohmic contact layer 26 to correspond to the gate electrode 15, and spaced apart from each other. In this case, the gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38, which may be sequentially stacked on the switching region TrA, may constitute the TFT.
Furthermore, a passivation layer 42 including a drain contact hole 45 exposing the drain electrode 38 may be formed on the entire surface of the resultant structure to cover the source and drain electrodes 36 and 38 and the exposed active layer 22. A pixel electrode 50 may be separately formed in each of pixel regions P on the passivation layer 42 and in contact with the drain electrode 38 through the drain contact hole 45. In this case, a semiconductor pattern 29 having a double structure including a first pattern 27 and a second pattern 23 may be formed under the data lines 33. The semiconductor pattern 29 may be formed of the same material as the ohmic contact layer 26 and the active layer 22.
On analysis of the semiconductor layer 28 of the TFT formed in the switching region TrA of the conventional array substrate 11 having the above-described structure, it can be seen that a portion of the active layer 22 formed of intrinsic amorphous silicon over which the ohmic contact layer 26 is formed apart from the active layer 22, is formed to a first thickness t1, and another portion of the active layer 22, which is exposed by removing the ohmic contact layer 26, has a second thickness t2 different from the first thickness t1. A difference (t1≠t2) in the thickness of the active layer 22 may be due to a manufacturing process. Due to the difference (t1≠t2) in the thickness of the active layer 22, more specifically, due to a reduction in the thickness of a portion of the active layer 22, which is exposed between the source and drain electrodes 36 and 38 and where a channel layer will be formed, characteristics of the TFT are degraded.
As a result, as shown in FIG. 2, which is a cross-sectional view of one pixel region of a conventional array substrate including a TFT having an oxide semiconductor layer, a TFT including an oxide semiconductor layer 80 having a single structure has lately been developed using an oxide semiconductor material without the need of an ohmic contact layer.
Since the oxide semiconductor layer 80 does not need the ohmic contact layer, unlike the conventional array substrate (refer to 11 in FIG. 1) including the active layer (refer to 22 in FIG. 1) formed of intrinsic amorphous silicon, it is unnecessary to expose the oxide semiconductor layer 80 to a dry etching process to form the ohmic contact layer (refer to 26 in FIG. 1), which is formed of impurity doped amorphous silicon, such that degradation of the characteristics of the TFT Tr may be prevented.
Meanwhile, LCDs having the above-described structure have lately been used for personal portable terminals, such as portable phones and personal digital assistants (PDAs). LCDs used for compact portable terminals may have smaller sizes than LCDs used for televisions (TVs) or monitors.
Accordingly, when the same resolution is embodied, the size of each of pixel regions constituting a display region may be relatively reduced.
Due to the above-described constructive characteristics, in an array substrate of an LCD used for compact portable terminals, the ratio of the area of a TFT in each of the pixel regions to the area of each of the pixel regions is relatively high.
Therefore, since the TFT has a relatively high parasitic capacitance due to overlap between a gate electrode and source/drain electrodes, a variation ΔVp in a kick-back voltage or feed-through voltage may also increase. As a result, degradation of charging characteristics of a pixel electrode, flickers, vertical crosstalk, and residual images may occur, thereby deteriorating resolution characteristics.
Furthermore, as shown in FIG. 3, which is a plan view of one pixel region of a conventional array substrate for an LCD including a TFT UTr having a rotated U-shaped channel, in the conventional array substrate for the LCD, the TFT UTr may have a U-shaped or rotated U-shaped channel to improve characteristics of the TFT UTr and increase an overlay margin. The TFT UTr having a U-shaped channel structure may reduce a variation in parasitic capacitance between a gate electrode 90 and source/drain electrodes 93 and 94 caused by process errors.
However, when the TFT including an oxide semiconductor layer has the U-shaped or rotated U-shaped channel structure, the area of an etch stopper may increase, so the oxide semiconductor layer disposed outside the etch stopper should be configured to contact the source/drain electrodes 93 and 94. As a result, the area of the TFT UTr may increase.
When the area of the TFT TUr increases, the aperture ratio of the pixel region may be reduced, and the entire parasitic capacitance caused by overlap between the gate electrode 90 and the source/drain electrodes 93 and 94 may also substantially increase.
Accordingly, when the TFT UTr including the U-shaped channel is formed on an array substrate for LCDs for compact portable terminals, the aperture ratio of the pixel region decreases.
In addition, since the overlap area between the gate electrode 90 and the source/drain electrodes 93 and 94 further increases relatively in the TFT UTr having the U-shaped channel structure, parasitic capacitance Cgs caused by overlap between the gate electrode 90 and the source/drain electrodes 93 and 94 may further increase relatively, thereby further deteriorating resolution characteristics.